Coarse-Grained Data Processor Having Both Global and Direct Interconnects

ABSTRACT

A data processor having a plurality of coarse-grained data processing elements arranged in rows and columns, an interconnect structure comprising both global and direct interconnects, the global interconnects interconnecting the coarse-grained data processing elements globally and the direct interconnects interconnecting adjacent data processing elements.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims priority to U.S. patentapplication Ser. No. 12/389,274, filed on Feb. 19, 2009, which is acontinuation of U.S. patent application Ser. No. 10/570,173, filed onNov. 10, 2006, which is the national stage of International ApplicationSerial No. PCT/EP04/09640, filed on Aug. 30, 2004, which claims priorityto German Patent Application Serial No. DE 030 19 428.6, filed on Aug.28, 2003, the entire contents of each of which are expresslyincorporated herein by reference.

FIELD OF INVENTION

The present invention relates to reconfigurable computing. Inparticular, the present invention relates to improvements in thearchitecture of reconfigurable devices.

BACKGROUND INFORMATION

Reconfigurable data processing arrays are known in the art. Reference isbeing made to the previous applications and/or publications of thepresent applicant/assignee all of which are incorporated herein by wayof reference. Accordingly, the devices described hereinafter may bemultidimensional (n>1) arrays comprising coarse grained computing and/ordata operation elements allowing for runtime reconfiguration of theentire array or parts thereof, preferably in response to a signalindicating reconfigurability to a loading unit (CT, CM or the like).

Now, several of these data processing arrays have been built (i.e. Xpp1,XPP128, XPP2, XPP64). It is however desirable to improve the knowndevice further as well as to improve methods of its operation.

SUMMARY OF THE INVENTION

Accordingly, in order to achieve this object there will be described anumber of improvements allowing separately or in common to improve theperformance and/or power consumption and/or cost of the device.

A first way to improve the known devices is to improve the functionalityof each single processor element. It has been previously suggested toinclude a ring-memory (RINGSPEICHER) in the array, to store instructionsin the ring-memory and to provide a pointer that points to one of thering-memory addresses so as to select an instruction to be carried outnext. Furthermore, it has been suggested to provide at least one “shadowconfiguration” and to switch over between several configurations/shadowconfigurations. Another or additional suggestions has been designated as“wave reconfiguration”.

While these known methods improve the performance of a reconfigurabledevice, there seems to be both a need and a possibility for furtherimprovements.

It is to be understood that while in the following description, adetailed example is given, for example with respect to the number ofregisters given associated with each PAE, it is not deemed necessary toprovide an ALU with exactly this number of registers. Rather, it will beunderstood by the average skilled person that deviations from theexplicitly described embodiment are easily feasible and that thedetailed level of description stems from an effort to provide anexemplary PAE and not from the wish to restrict the scope of invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an ALU-PAE architecture.

FIG. 2 shows function folding.

FIG. 3 shows a sequencer model.

FIG. 4 shows Method A: FF PAE program pointer.

FIG. 5 shows Method B: FF PAE program pointer.

FIG. 6 shows a test logic.

FIG. 7 shows an overview of the entire circuitry of FIGS. 5 and 6.

FIG. 8 shows a VPU architecture.

FIG. 9 shows a PAE implementation.

FIG. 10 shows a bus system.

FIG. 11 shows a modified PAE structure.

FIG. 12 shows an ALU-PAE having inputs and outputs in both directions.

FIG. 13 shows a modified bus system.

FIG. 14 shows a PAE exchanging data without latency.

FIG. 15 shows an optimised PAE arrangement.

FIG. 16 shows superscalar FF ALU-PAEs.

FIG. 17 shows a datapath architecture.

FIG. 18 shows another datapath architecture.

FIG. 19 shows a configurable sequencer.

FIG. 20 shows an enhanced version of an ALU-PAE.

FIG. 21 shows an overview of the RAM-PAE.

FIG. 22 shows PAE Structure and Arrangement V2.0 and PAE Structure andArrangement V2.2.

FIG. 23 shows an enhanced DF or Bypass (PB) part within the PAEs.

FIG. 24 shows an enhancement of RAM-PAEs.

FIG. 25 shows a memory organization.

FIG. 26 shows another memory organization.

FIG. 27 shows address generators.

FIG. 28 shows a parameter stack mode.

FIG. 29 shows multi-config mode.

FIG. 30 shows multi-config mode for long configurations.

FIG. 31 shows parameter broadcast and update.

FIG. 32 shows code bank, data bank, stack bank, and auxiliary bank.

FIG. 33 shows the memory layout.

FIG. 34 shows the memory layout.

FIG. 35 shows an advanced valid checking scheme.

FIGS. 36 to 44 show an improved way of routing.

FIG. 45 shows a simplified structure of an XPP array.

FIG. 46 shows a function folding processing element.

FIGS. 47A and 47B show an address generation data flow graph.

FIG. 48 shows an extended XPP tool flow.

FIGS. 49A and 49B show a complex FIR filter cell.

FIG. 50 shows data and control flow.

FIG. 51 shows a PAE-like Petri-Net.

FIG. 52 shows data duplication in the output path of the Petri-Net.

DETAILED DESCRIPTION 1 Overview of Changes vs. XPP XPP-II 1.1 ALU-PAEArchitecture

In the suggested improved architecture, a PAE might e.g. comprise 4input ports 100 and 4 output ports 104. Embedded with each PAE is theFREG path newly named DF 135 with its dataflow capabilities, like MERGE,SWAP, DEMUX as well as ELUT.

2 input ports Ri0 and Ri1 are directly connected to the ALU.

Two output ports receive the ALU results.

Ri2 and Ri3 are typically fed to the DF path which output is Ro2 andRo3.

Alternatively Ri2 and Ri3 can serve as inputs for the ALU as well. Thisextension is needed to provide a suitable amount of ALU inputs ifFunction Folding (as described later) is used.

In this mode Ro2 and Ro3 serve as additional outputs.

Associated to each data register (Ri or Ro) is an event port (Ei or Eo).

It is possible, albeit not necessary to implement an additional data andevent bypass BRi0-1 125, BEi0-. The decision depends on how oftenFunction Folding will be used and how many inputs and outputs arerequired in average.

(see FIG. 1 now)

1.1.1 Other Extensions

SIMD operation is implemented in the ALUs to support 8 and 16 bit widedata words for i.e. graphics and imaging.

Saturation is supported for ADD/SUB/MUL instructions for i.e. voice,video and imaging algorithms.

1.2 Function Folding 1.2.1 Basics and Input/Output Paradigms

Within this chapter the basic operation paradigms of the XPParchitecture are repeated for a better understanding based onPetri-Nets. In addition the Petri-Nets will be enhanced for a betterunderstanding of the subsequently described changes of the current XPParchitecture.

In most arrays each PAE operates as a data flow node as defined byPetri-Nets. (Some arrays might have parts that have other functions andshould thus be not considered as a standard PAE). A Petri-Net supports acalculation of multiple inputs 5200 and produces one single output 5202.Special for a Petri-Net is that the operation is delayed until all inputdata is available.

For the XPP technology this means:

-   -   1. all necessary data is available    -   2. all necessary events are available

The quantity of data—and events is defined by the data and control flow,the availability is displayed at runtime by the handshake protocolRDY/ACK.

(see FIG. 50 now)

Here, the thick arbor indicates the operation, the dot on the right sideindicates that the operation is delayed until all inputs 5300 areavailable.

Enhancing the basic methodology function folding supports multipleoperations—maybe even sequential—instead of one, defined as a Cycle. Itis important that the basics of Petri-Nets remain unchanged.

(see FIG. 51 now)

Here, typical PAE-like Petri-Nets consume one input packet 5400 per oneoperation. For sequential operation multiple reads of the same inputpacket are supported. However, the interface model again keepsunchanged.

Data duplication occurs in the output path 5402 of the Petri-Net, whichdoes not influence the operation basics again.

(see FIG. 52 now)

1.2.2 Method of Function Folding

One of the most important extensions is the capability to fold multiplePAE functions onto one PAE and execute them in a sequential manner. Itis important to understand that the intention is not to supportsequential processing or even microcontroller capabilities at all. Theintention of Function Folding is just to take multiple dataflowoperations and map them on a single PAE, using a register structureinstead, of a network between each function.

One goal may be to save silicon area by rising to clock frequencylocally in the PAE's. An additional expectation is to save power sincethe busses operate at a fraction of the clock frequencies of the PAEs.Data transfers over the busses, which consume much power, are reduced.

(see FIG. 2 now)

The internal registers can be implemented in different ways, e.g. in oneof the following two:

1. Dataflow Model

Each register (r′) has a valid bit which is set as soon as data has beenwritten into the register and reset after the data has been read. Datacannot be written if valid is set, data can not-be read if valid is notset. This approach implements a 100% compatible dataflow behaviour.

2. Sequencer Model

The registers have no associated valid bits. The PAE operates as asequencer, whereas at the edges of the PAE (the bus connects) theparadigm is changed to the XPP-like dataflow behaviour.

Even if at first the dataflow model seems preferable, it has major downsides. One is that a high amount of register is needed to implement eachdata path and data duplication is quite complicated and not efficient.Another is that sometimes a limited sequential operation simplifiesprogramming and hardware effort.

Therefore it is assumed consecutively that sequencer model isimplemented. Since pure dataflow can be folded using automatic tools theprogrammer should stay within the dataflow paradigm and not be confusedwith the additional capabilities. Automatic tools must take care i.e.while register allocation that the paradigm is not violated.

FIG. 3 now shows that using sequencer model only 2 registers (instead of4) are required.

For allowing complex function like i.e. address generation as well asalgorithms like “IMEC”-like data stream operations the PAE has not only4 instruction registers implemented but 8, whereas the maximum bus-clockvs. PAE-clock ration is limited to a factor of 4 for usual functionfolding.

It is expected that the size of the new PAE supporting Function Foldingwill increase by max. 25%. On the other hand 4 PAEs are reduced to 1.

Assuming that in average not the optimum but only about 3 functions canbe folded onto a single PAE a XPP64 could be replaced by a XPP21. Takingthe larger PAEs into account the functionality of a XPP64 XPP-II shouldbe executable on a XPP XPP-III with an area of less than half.

The function folding method and apparatus as well as other furtherimprovements will be described in even more detailed hereinafter.

Equality of Internal Data Registers and Bus Transfers

The function fold concept realizes two different models of dataprocessing:

-   -   a) Sequential model, wherein within the PAE the same rules apply        as in von-Neuman- and Harvard-processors.    -   b) PACT VPU-model, wherein data are calculated or operated upon        in arbitrary order according to the PETRI-Net-Model (data        flow+synchronization).

Due to the unpredictability of the arrival of data at the inputregisters (IR) a deadlock or at a least significant reduction inperformance could occur if the commands in RC0 . . . RCn 108 were to beperformed in a linear manner. In particular, if feed-backs of the PAEoutputs to the inputs of the PAE are present, deadlocks might occur.This can be avoided if the instructions are not to be processed in agiven order but rather according to the possibility of their processing,that is, one instruction can be carried out as soon as all conditions ofthe VPU-model are fulfilled. Therefore, for example, once allRDY-handshakes of incoming data, ACK-handshakes of outgoing data and, ifnecessary, triggers, (including their handshakes) are valid, then theinstruction can be carried out. As the FF PAE has data additionallystored in internal registers, their validity and status has to becheckable as well in a preferred embodiment. Therefore, every internaldata register (RD0 . . . RDn) 110 is separately assigned a valid bitindicating whether or not valid data are present in the register. Whenwriting data into the register, valid is set; when reading, valid isreset. Data can be read only if “valid” is set and can be written onlyif “valid” is not set. Accordingly, the valid flag corresponds mostclosely to the status that is produced in the state machines of bussystems by the transmittal of RDY/ACK-handshakes. It is a preferredembodiment and considered to be inventive to provide a register with astatus bit in that way.

It is therefore possible to carry out instructions at the time when allconditions for the execution—again very similar to PETRI-nets arefulfilled.

Basically, there are two methods available for selection of instructionand control of their execution described herein after.

Method a: FF PAE Program Pointer (Finite State Machine & ProgramPointer—Approach)

(see FIG. 4 now)

According to the control principle of sequential processors, a programcounter is used to select a certain instruction within the instructionmemory. A finite state machine 400 controls the program counter. Thisfinite state machine now checks whether or not all conditions for theinstruction in RC (PC), that is the instruction, onto which the PC.(Program Counter) 402 points, are fulfilled. To do so, the respectiveRDY- and/or ACK-handshakes of the in- and/or outputs needed for theexecution of the instructions are checked. Furthermore, the valid-flagsof the internal registers to be read (RD0 . . . RDn) 404 are checked soas to control whether or not they are set, and the valid-flags of thoseinternal registers (RD0 . . . RDn) into which is to be written, arechecked whether they are not set. If one of the conditions is notfulfilled, the instructions will not be carried out. PC is controlled tocount further, the instruction is skipped and the next instruction isselected and checked as described.

The advantage of this method is the compatibility with sequentialprocessor models. The disadvantage resides in the necessity to test andto skip instructions. Both of which might result in significant lossesof performance under certain circumstances.

Method B: FF PAE Program Pointer (Enabler & Arbiter-Approach)

(see FIG. 5. now)

This method is based upon the possibility to test all instructions inRc0 . . . Rcn 502 in parallel. In order to save the expense of thecomplete decoding of array instructions, each RC is assigned an entry inan evaluation mask field, the length of which corresponds to the maximumnumber of states to be tested; therefore, for every possible RDY- orACK-trigger-signal (as well the RDY/ACKs of the triggers) as well as forevery valid bit in RD0 . . . RDn 404 two bits are available indicatingwhether or not the respective signal is to be set or not set; or,whether the state of the signal is unimportant for the execution of theinstruction.

InData-RDY OutData-ACK InTrigger OutTrigger-ACK Rd Data Valid Rdy don'tAck don't trigger rdy don't ack don't valid don't value care value carevalue value care value care value care

The mask shows only some entries. At In-Trigger, both the state of thetrigger (set, not set) as well as the value of the trigger (triggervalue) can be tested via RDY-value.

A test logic testing 500 via for example the Line Control describedherein after all instructions in parallel. Using an arbiter 650, aninstruction of the set of all executables is selected. The arbitercontrols the instruction multiplexer via ISel according to thetransferral of the selected instructions to the PAE.

The Line Control has one single line of Boolean test logic for everysingle instruction. By means of an ExOR-gate (e) 600 the value of thesignal to be tested against the setting in em of the line is checked. Bymeans of an OR-gate (+) 602 respectively, a selection is carried out,whether the checked signal is relevant (don't care). The results of allchecked signals are ANDed. A logic 1 at the -output of the AND-gates (&)604 shows an executable instruction. For every RC, a different test-lineexists. All test-lines are evaluated in parallel. An arbiter having oneof a number of possible implementations such as a priority arbiter,Round-Robin-Arbiter and so forth, selects one instruction for executionout of all executable instructions. There are further implementationspossible obvious to the average skilled person. Those variants might bewidely equivalent in the way of operation and function. In particular,the possibility of using “negative logic” is to be mentioned.

(see FIG. 6 now)

FIG. 7 now gives an overview of the entire circuitry.

Advantages of the method are:

-   -   Significantly fast, in view of the fact that one instruction can        be carried out in every single clock    -   Reduced power consumption, since no energy is wasted on        discarded cycles which is in particular advantageous to the        static power dissipation.    -   Similar hardware expense as in the sequential solution when        using small and medium sized configuration memories (RC)        therefore similar costs.

Disadvantages:

-   -   Likely to be significantly more expensive on large RC;        therefore, an optimisation is suggested for a given set of        applications.    -   In order to implement the sequencer mode (compare other parts of        the application) the program counter having an FSM must be        provided for. The FSM then is restricted to the tasks of the        sequencer so that the additional expenses and the additional        costs are relatively low.

Depopulated Busses According to the State of the Art

All busses assigned to a certain PAE are connected to the inputregisters (IR) or the output registers of the PAE are connected to allbusses respectively (compare for example DE 100 50 442.6 or theXPP/VPU-handbooks of the applicant).

It has been realised that PAEs, in particular FF PAEs, allow for adepopulation of bus interconnects, in particular, if more IR/OR will beavailable compared to the State of the Art of the XPP as previouslyknown. The depopulation, that is the reductions of the possibilities toconnect the IR or ER onto the busses can be symmetrically orasymmetrically. The depopulation will typically amount to 20 to 70%. Itis significant that the depopulation will not or not significantlyaffect the interconnectability and/or the routability of an algorithm ina negative way.

The method of depopulation is particularly relevant in view of the factthat several results can be achieved. The hardware-expense and thus thecosts of the bus systems can be reduced significantly; the speed of thebusses is increased since the gate delay is reduced by the minimisationof connecting points; simultaneously, the power consumption of thebusses is reduced.

A preferred depopulation according to the VPU-architecture according tothe State of the Art, however, with more IR/OR is shown in FIG. 8 now.

In particular, reference is being made to an optional extension of thebus architecture allowing for a direct next neighbour data transfer oftwo adjacent PAEs, in particular two PAEs placed one onto the other.Here, the outputs (OR) of one PAE are directly connected to a dedicatedbus which is then directly connected to the inputs (IR) of aneighbouring PAE (compare FIG. 9 now). The figure only shows ahorizontal next neighbour bus, however, in general, vertical busses arepossible as well.

In FIG. 8 now, the shaded circles stand for possible bus connects: MUX.Double circuits stand for a connection from the bus: DeMUX.

Changes of the PAE IO

FIG. 9 now shows the State of the Art of a PAE implementation as knownfrom XPU 128, XPP64A and described in DE 100 50 442.6

The known PAE has a main data flow in the direction from top to bottomto the main ALU 10 in the PAE-core. At the left and right side, datachannels are placed additionally transmitting data along the main dataflow direction, once the same direction as the main data flow (FREG) 800and once in the reverse direction (BREG) 802. On both sides of the PAE,data busses are provided that run in the reverse direction of the maindata flow of the PAE and onto which the PAE as well as FREG and BREG areconnected. The architecture of the State of the Art requires eight databusses for each PAE side as well as four transfer channels for FREG/BREGfor typical applications.

The bus system of the State of the Art has switching elements, registerelements (R) 1000, each at the side of the PAEs. The switching elementsallow for the disruption of a bus segment or disconnection to aneighbouring bus, the register elements allow the construction of anefficient pipelining by transferring data through the register, so as toallow for higher transferral band-width. The typical latency in verticaldirection for next-neighbour-transmitting is 0 per segment, however is0.5-1 in horizontal direction per segment and higher frequencies.

(see FIG. 10 now)

Now, a modified PAE structure is suggested, wherein two ALUs 10 a, 10 b,each having a different main data flow direction are provided in eachPAE, allowing for significantly improved routability. On one hand, thetools used for routing are better and simpler; on the other hand, asignificant reduction in hardware resources is achieved. First testsshow that the number of busses necessary in horizontal direction isreduced by about 25% over the State of the Art. The vertical connects inFREG/BREG (=BYPASS) can even be reduced by about 50%. Also, it is nomore necessary to distinguish between FREG and BREG as was necessary inDE 100 50 442.6.

(see FIG. 11 now)

The double-ALU structure has been further developed to an ALU-PAE 10having inputs and outputs in both directions. Using automatic routers aswell as hand-routed applications, further additional significantimprovements of the network topology can be shown. The number of bussesnecessary seems to be reduced to about 50% over the State of the Art,the number of vertical connects in the FREG/BREG (=BYPASS) can bereduced by about 75%.

(see FIG. 12 now)

For this preferred embodiment which can be used for conventional as wellas for function fold ALUs, it is possible to place register andswitching elements 1000 in the busses in the middle of the PAE insteadof at the sides thereof (see FIG. 13 now).

In this way, it is possible even for high frequencies to transmit datain horizontal direction to the respective neighbouring PAE withouthaving to go through a register element. Accordingly, it is possible toset, up next neighbour connections in vertical and horizontal directionswhich are latency free (compare State of the Art and drawings referringto depopulated busses). The example of the interconnections shown in therespective figure allows transferral having zero latency in verticaldirection and horizontally from left to right. Using an optimisation ofPAE interface structure a latency free next neighbouring transmission inboth horizontal directions can be achieved. If in every corner of thePAE input register (IR, arrow of bus into PAE) 1405 from bus and outputregister (OR, arrow from PAE to bus) 1400 to the bus are implemented,each neighbouring PAE can exchange data without latency.

(see FIG. 14 now)

It is possible to further optimise the above disclosed PAE arrangement.This can be done by using no separate bypass at all in all or some ofthe PAEs. The preferred embodiment comprises two ALUs 1500, 1502, one ofthese being “complete” and having all necessary functions, for examplemultiplication and BarrelShift while the second has a reducedinstruction set eliminating functions that require larger arrays such asmultiplication and BarrelShift. The second ALU is in a way replacingBYPASS (as drawn). There are several possible positions for the registerin switching elements per bus system, and two of the preferred positionsper bus are shown in FIG. 15 in dotted lines.

Both ALUs comprise additional circuits to transfer data between thebusses so as to implement the function of the bypass. A number ofpossible ways of implementations exist and two of these shall beexplained as an example.

a) Multiplexer

Configurable multiplexers within the ALU are connected so that ALUinputs are bypassing the ALU and are directly connected to theiroutputs.

b) MOVE Instruction

A MOVE instruction, stored in Rc0 . . . Rcn is transferring within therespective processing clock of the function fold the data according tothe input specified within the instruction to the specified output.

Superscalarity/Pipelining

It is possible and suggested as first way of improving performance toprovide roughly superscalar FF ALU-PAEs which calculate for example 2,4, 8 operations per bus clock @ FF=2, 4, 8, even while using the MULopcode.

The basic concept is to make use of the VALID-flags of each internalregister. MUL is implemented as one single opcode which is pipelinedover two stages.

MUL 1704 takes its operands from the input registers Ri and stores theresults into internal data registers Rd. VALID is set if data is storedinto Rd. ADD (or any other Opcode, such as BSFT 1706) uses the result inRd if VALID is set; if not the execution is skipped according to thespecified VALID behaviour. In addition the timing changes for allOpCodes, if the MUL instruction is used inside a PAE configuration. Inthis case all usually single cycle OpCodes will change to pipelined 2cycle, OpCodes. The change is achieved by inserting a bypass ablemultiplexer into the data stream as well as into control.

The following program will be explained in detail:

-   -   MUL (Rd0, Rd1), Ri0, Ri1;    -   ADD Ro0, Rd1, Ri2;

In the first bus-cycle after configuration (t₀) MUL is executed(assuming the availability of data at Ri0/1). The register pair Rd0/1 isinvalid during the whole bus-cycle, which means during both FF-PAEinternal clock cycles. Therefore ADD is not executed in the 2^(nd) clockcycle. After t₀ the result of MUL is written into the register pair,which VALID flags are set at the same time.

In t₁ new data is multiplied. Since the VALID is set for Rd0/1 now theADD command is executed in the 2^(nd) clock cycle, but takes 2 clockcycles for over all execution. Therefore operand read and result writeis inline for both operations, MUL as well as ADD.

The result of a MUL-ADD combination is available with 2 clocks latencyin a FF=2 ALU-PAE. For FF>=6 no latency is inserted.

(see FIG. 16 now)

However since multiplication and all other commands are processed inparallel the machine streams afterwards without any additional delays.

(see FIG. 17 now)

If there are OpCodes besides MUL which require 2 clock cycles forexecution (e.g. BSTF) the architecture must be modified to allow atleast 3 data writes to registers after the second internal clock cycle.

The data path output multiplexer gets 2 times larger as well as the bussystem to the output registers (OR) 1702 and the feedback path to theinternal data registers (Rd).

If accordingly defined for the OpCodes, more than 4 internal registerscan be used without increasing the complexity by using enables (en) toselect the specific register to write in the data. Multiple registersare connected to the same bus, e.g. Rd0, Rd4, Rd8, Rd12. However not allcombinations of register transfers are possible with this structure. Ife.g. MUL uses Rd0 and Rd1 the following registers are blocked for theOpCode executed in parallel: Rd4, 5, 8, 9, 12, 13.

Register Map:

Rd0 Rd1 Rd2 Rd3 Rd4 Rd5 Rd6 Rd7 Rd8 Rd9 Rd10 Rd11 Rd12 Rd13 Rd14 Rd15Datapath Architecture: See FIG. 18 Now. The Sequencer PAEs

Since there is a need to be able to run control flow dominatedapplications on the XPP III as well, Sequencer PAEs will be introduced.Such a PAE can be thought of as a very simple kind of processor which iscapable to run sequential code within the XPP. This allows the efficientimplementation of control flow oriented applications like the H.264Codec on the array whereas with SEQ-PAEs missing the realization wouldbe more difficult and resource consuming.

The SEQ-PAEs are not built from scratch. Instead such a tile will bebuilt up by a close coupling of a ALU-PAE 1902 and neighboring RAM-PAE1900, which can be seen in FIG. 19 now.

Therefore the functionality of the ALU—as well as RAM-PAE has to beenhanced to be able to fulfill the requirements of such a SEQ-PAE. Thisinformation will be given next.

ALU-PAE Enhancements

The extended version of the ALU-PAE is given in FIG. 20 now. To theright border the registers which are controlling the different modulescan be seen. Those registers will be used in normal—as well as inSEQ-mode. Therefore the appropriate control signals from the localconfiguration manager and the RAM-PAE are first merged by OR-Gates andthen are forwarded to the register whereas it has to be ensured that innormal mode the signals from the RAM-PAE are 0 and vice versa.

Furthermore, since the ALU-PAE marks the execution part of the tinyprocessor, there is a need to transfer values to and from the internalregister directly to the RAM. Therefore, an additional multiplexer AM12000 is inserted in the multiplexer hierarch of section 2. In the normalmode this multiplexer feeds the word from its predecessor to the nextstage whereas in the SEQ mode an immediate value provided by the Imm.Register will be delivered. In addition in SEQ mode a value of one ofthe internal registers can be delivered to the RAM-PAE via the output ofthe multiplexer. However, it has also to be considered to provide a“LOAD reg, imm” since this is not much slower than “ADD reg, reg, imm”

To enable the RAM-PAE to write data to the internal register of theALU-PAE another multiplexer is inserted in the multiplexer chain ofsection 4. Similar to the scenario given above this multiplexer willonly be activated in SEQ mode whereas in normal mode this multiplexerwill just forward the data of its predecessor. In one preferredembodiment, it is suggested to place RS2 behind BSFT-Mux in view of thedelay. Data could be written into the internal registers via this. (LOADreg, imm)]

As it has already been discussed, data can be processed during one ortwo cycles by the ALU-PAE depending on the selected arithmetic function.Due to the auto synchronization feature of the XPP and due to the factthat in normal mode a successive operation will not start before theprevious one is finished, it does not really care if an operation lastsone or two clock cycles. Whereas the tile is working in SEQ mode thereis a difference since we assume to have a pipeline character. This meansthat a one cycle operation could run in parallel with a two cycle modulewhere the operation would be executed in stage two at this time. Due tothe limited multiplexing capacities of a word—16 Bit—only one resultcould be written to the connected registers whereas the other one wouldbe lost. In general there are three possibilities to solve this problem.

The first one could be that the compiler is capable to handle thisproblem. This would mean that it has to know about the pipelinestructure of the whole SEQ-PAE as well as of a tile in detail. Toprohibit a parallel execution the compile would have to add a NOP toevery two cycle instruction for the structure given above. However thisidea seems not to be convenient due to the strong relation between thehardware structure and the compiler. The drawback would be that everytime changes are made to the hardware the compile would most likely haveto be trimmed to the new structure.

The second idea could be to recognize such a situation in the decodestage of the pipeline. If a two cycle instruction is directly followedby an instruction accessing a one stage arithmetic unit it has to bedelayed by one clock cycle as well.

The last possibility is to make the complete ALU-PAE look like a twostage execution unit. Therefore only one register has to be included inthe multiplexer chain of section four right after the crossover from themultiplexer separating the one stage of the two stage modules.Obviously, this is preferred.

Comparing the last to ideas the third one seems to be the best one sinceonly one register has to be inserted If we a closer look to the secondsolution special logic would be needed for analyzing the disallowedcombination of instructions as well as logic for stopping the programcounter (PC) and the instruction retardation. It has to be assumed thatthis logic would require much more area than the registers as well asthe fact that the delay of the logic would possibly increase thecritical path.

Since it has to be distinguished between the SEQ and the normal modewhere a one cycle execution should still be available. This possibilityis given by a multiplexer which allows bypassing the RS2 Register asshown in the corresponding figure (FIG. 20 now).

the RAM-PAE A Short Description of the Stages

To get the SEQ-PAE working there still has to be provided morefunctionality. Right now the RAM-PAE 2100 will take care of it. As afirst approach for realizing the sequencer a four stage pipeline hasbeen chosen. The stages are, as it can be seen in FIG. 21 now:

-   -   The fetch stage 2102    -   The decode stage 2104    -   The execution stage 1 2106    -   The execution stage 2 2108

In the fetch stage the program counter for the next clock cycle will becalculated. This means that it will be either incremented by 1 via alocal adder or one of the program counters from the decode or executionstage 2 will be selected. The program counter of the execution stagethereby provides the address if a call instruction occurred whereas theprogram counter of the execution stage provides the PC if there has beena conditional jump. Right now the branch address can either becalculated out of the current PC and a value which either is animmediate value or a value from internal registers of theALU-RAM—indirect addressing mode—or an absolute value. This e.g. isnecessary if there is return from a subroutine to the previous contextwhereas the according absolute PC will be provided by the stack bank.

In the decode stage the instruction coming from the code bank will bedecoded. Necessary control signals and, if needed, the immediate value,for the internal execution stage 1 as well as for the execution stage 1of the ALU-PAE will be generated. The signals include the controlinformation for the multiplexers and gating stages of section two of theALU-PAE, the operation selection of the ALU's tiles, e.g. signed orunsigned multiplication, and the information whether the stack pointer(SP) should be in/decremented or kept unchanged in the next stagedepending on the fact if the instruction is either a call or jump. Incase a call instruction occurred a new PC will be calculated in paralleland delivered to the fetch stage.

Furthermore the read address and read enable signal to the data bankwill be generated in case of a load instruction. In the execution stage1, which by the way is the first stage available on the ALU as well ason the RAM-PAE, the control signals for execution stage 2 of the ALU-PAEare generated. Those signals will take care that the correct output ofone of the arithmetical tiles will be selected and written to theenabled registers. If the instruction should be a conditional jump orreturn the stack pointer will be modified in this stage. In parallel theactual PC will be saved to the stack bank at the address give by the RspEX1 register in case of a branch. Otherwise, in case of a return, theread address as well as the read enable signal will be applied to thestack bank.

In execution stage 2 the value of the PC will be calculated and providedto the multiplexer in the fetch stage in case of a jump. At the timewrite address and write enable signal to the data bank are generated ifdata from the ALU have to be saved.

Instead of two adders, it is possible to provide only one in the rpppath.

Pipeline Actions

In the following section a short overview of the actions that are takingplace in the four stages will be given for some basic instructions. Itshould help to understand the behaviour of the pipeline. Since theinstruction which is going to be discussed will be available at theinstruction register the actins of the fetch stage will be omitted inthis representation.

IR: Instruction Register DR: Data Register DB: Data Bank SBR:Store/Branch Register

Instruction: Load Value from Data Bank to R[n]

ALU-PAE RAM-PAE decode stage IR_ex1 <- IR_ex2 Control Registerset EXS1<- 0 × 0 Imm. EXS1 <- 0 × 0 Rpp_ex1 <- Rpp_de DB_radr <0 imm Executionstage 1 IR_ex2 <- IR_ex1 Control Registerset EXS2 <- enable R, set muxsection 4 Rpp_ex2 <- Rpp_ex1 DR <- DB_radr [imm] Rsp_ex2 <- Rsp_ex1Execution stage 2 R[n] <- DRInstruction: Store Value from R[n] to Data Bank

ALU-PAE RAM-PAE decode stage IR_ex1 <- IR_ex2 Control Registerset EXS1<- enable mux section 2 Imm. EXS1 <- 0x0 Rpp_ex1 <- Rpp_de Executionstage 1 SBR <- R[n] 1R_ex2 <- IR_ex1 Control Registerset EXS2 <- 0x0Rpp_ex2 <- Rpp_ex1 Rsp_ex2 <- Rsp_ex1 Execution stage 2 DB_wradr <- immDB_wrdata <- SBR

1.3 Array Structure

First advantages over the prior art are obtained by using functionfolding PAEs. These as well as other PAEs can be improved.

The XPP-II structure of the PAEs consumes much area for FREG and BREGand their associated bus interfaces. In addition feed backs through theFREGs require the insertion of registers into the feedback path, whichresult not only in an increased latency but also in a negative impactonto the throughput and performance of the XPP.

A new PAE structure and arrangement is proposed with the expectation tominimize latency and optimize the bus interconnect structure to achievean optimized area.

The XPP-III PAE structure does not include BREGs any more. As areplacement the ALUs are alternating flipped horizontally which leads toimproved placement and routing capabilities especially for feedbackpaths i.e. of loops.

Each PAE contains now two ALUs and two BP paths 2200, one from top tobottom and one flipped from bottom to top.

(see FIG. 22 now)

1.4 Bus Modifications

Within this chapter optimizations are described which might reduce therequired area and the amount of busses. However, those modificationscomprise several proposals, since they have to be evaluated based onreal algorithms. It is possible to e.g. compose a questionnaire tocollect the necessary input from the application programmes.

1.4.1 Next Neighbour

In XPP-II architecture a direct horizontal data path between two PAEsblock a vertical data bus. This effect increases the required verticalbusses within a XPP and drives cost unnecessarily. Therefore in XPP-IIIa direct feed path between horizontal PAEs is proposed.

In addition horizontal busses-of different length are proposed, i.e.next neighbour, crossing 2 PAEs, crossing 4 PAEs.

1.4.2 Removal of Registers in Busses

In XPP-II registers are implemented in the vertical busses which can beswitched on by configuration for longer paths. This registers canfurthermore be preloaded by configuration which requires a significantamount of silicon area. It is proposed to not implement registers in thebusses any more, but to use an enhanced DF or Bypass (PB) part withinthe PAEs which is able to reroute a path to the same bus using the DF orBP internal registers instead.

(see FIG. 23 now)

Here, it might be to decide how many resources are saved for the bussesand how many are needed for the PAEs and/or how often must registers beinserted, are 1 or max. 2 paths enough per PAE (limit is two since DF/BPoffers max. 2 inputs)

1.4.3 Shifting n:1, 1:n Capabilities from Busses to PAEs

In XPP-II n:1 and 1:n transitions are supported by the busses whichrequire a significant amount of resources i.e. for the sample-and-holdstage of the handshake signals.

Depending on the size of n two different capabilities are provided withthe new PAE structure:

n ≦ 2 The required operations are done within the DF path of the PAE 2 ≦n ≦ 4 The ALU path is required since 4 ports are necessary n > 4Multiple ALUs have to be combined.

This method saves a significant amount of static resources in siliconbut requires dedicated PAE resources at runtime.

Here, it might be worthwhile to evaluate how much silicon area is savedper bus how often occurs n=2, 2≦n≦4, n>4 the ratio between saved siliconarea and required PAE resource and to decide on the exact bus structurein response to one or all of said criteria.

1.5 FSM in RAM-PAEs

In the XPP-II architecture implementing control structures is verycostly, a lot of resources are required and programming is quitedifficult.

However memories can be used for a simple FSMs implementation. Thefollowing enhancement of the RAM-PAEs offers a cheap and easy to programsolution for many of the known control issues, including HDTV.

(see FIG. 24 now)

Basically the RAM-PAE is enhanced by a feedback from the data output tothe address input through a register (FF) 2402 to supply subsequentaddress within each stage. Furthermore additional address inputs fromthe PAE array can cause conditional jumps; data output will generateevent signals for the PAE array. Associated counters 2404 which can bereloaded and stepped by the memory output generate address input forconditional jumps (i.e. end of line, end of frame of a video picture).

A typical RAM PAE implementation has about 16-32 data bits but only 8-12address bits. To optimize the range of input vectors it is thereforesuggested to insert some multiplexers at the address inputs to selectbetween multiple vectors, whereas the multiplexers are controlled bysome of the output data bits.

One implementation for an XPP having 24 bit wide data busses is sketchedin FIG. 25 now. 4 event inputs are used as input, as well as the lowerfor bits of input port Ri0. 3 counters are implemented, 4 events aregenerated as well as the lower 10 bits of the Ro0 port.

The memory organisation suggested here may be as follows:

-   -   8 address bits    -   24 data bits (22 used)        -   4 next address        -   8 multiplexer selectors        -   6 counter control (shared with 4 additional next address)        -   4 output        -   (see FIG. 25 now)

It is to be noted that the typical memory mode of the RAM-PAE is notsketched in the block-diagram mentioned above.

The width of the counters is according to the bus width of the databusses.

For a 16 bit implementation it is suggested to use the carry signal ofthe counters as their own reload signal (auto reload), also some of themultiplexers are not driven by the memory but “hard wired” by theconfiguration.

The proposed memory organisation is as follows:

-   -   8 address bits    -   16 data bits (16 used)        -   4 next address        -   4 multiplexer selectors        -   3 counter control (shared with 3 additional next address)        -   4 output        -   (see FIG. 26 now)

It is to be noted that actually the RAM-PAEs typically will not bescaleable any more since the 16-bit implementation is different from the24-bit implementation. It is to decide whether the striped down 16-bitimplementation is used for 24-bit als

1.6 IOAG Interface 1.6.1 Address Generators and Bit Reversal Addressing

Implemented within the IO interfaces are address generators 2700 tosupport e.g. 1 to 3 dimensional addressing directly without any ALU-PAEresources. The address generation is then done by 3 counters; each ofthem has e.g. configurable base address, length and step width.

The first counter (CNT1) has a step input to be controlled by the arrayof ALU-PAEs. Its carry is connected to the step input of CNT2, whichcarry again is connected to the step input of CNT3.

Each counter generates carry if the value is equal to the configuredlength. Immediately with carry the counter is reset to its configuredbase address.

One input is dedicated for addresses from the array of ALU-PAEs whichcan be added to the values of the counters. If one or more counters arenot used they are configured to be zero.

In addition CNT1 supports generation of bit reversal addressing bysupplying multiple carry modes.

(see FIG. 27 now)

1.6.2 Support for Different Word Width

In general it is necessary to support multiple word width within the PAEarray. 8 and 16 bit wide data words are preferred for a lot ofalgorithms i.e. graphics. In addition to the already described SIMDoperation, the IOAG allows the split and merge of such smaller datawords.

Since the new PAE structure allows 4 input and 4 output ports, the IOAGcan support word splitting and merging as follows:

I/O 0 I/O 1 I/O 2 I3 16/24/32-bit data address word 16-bit data word16-bit data word address  8-bit data word  8-bit data word 8-bit dataword address

Input ports are merged within the IOAG for word writes to the JO.

For output ports the read word is split according to the configured wordwidth.

1.7 Multi-Voltage Power Supply and Frequency Stepping

PAEs and busses are built to perform depending on the workload.Therefore the clock frequency is configurable according to the databandwidth, in addition clock gating for registers is supported, bussesare decoupled using row of AND gates. Dynamically clock pulses aregated, whenever no data can be processed.

Depending on the clock frequency in the PAEs and the required bandwidthfor the busses the voltage is scaled in an advanced architecture. Withinthe 4S project such methods are evaluated and commercially usabletechnologies are researched.

1.8 XPP/μP Coupling

For a closed coupling of a μP and a XPP a cache and register interfacewould be the preferable structure for high level tools like C-compilers.However such a close coupling is expected not to be doable in a veryfirst step.

Yet, two different kind of couplings may be possible for a tightcoupling:

-   -   a) memory coupling for large data streams: The most convenient        method with the highest performance is a direct cache coupling,        whereas an AMBA based memory coupling will be sufficient for the        beginning (to be discussed with ATAIR)    -   b) register coupling for small data and irregular MAC        operations: Preferable is a direct coupling into the processors        registers with an implicit synchronisation in the OF-stage of        the processor pipeline. However coupling via load/store- or        in/out-commands as external registers is acceptable with the        penalty of a higher latency which causes some performance        limitation.

2 Specification of ALU-PAE 2.1 Overview

In a preferred embodiment, the ALU-PAE comprises 3 paths:

-   -   ALU arithmetic, logic and data flow handling    -   BP bypass

Then, each of the paths contains 2 data busses and 1 event bus. Thebusses of the DF path can be rerouted to the ALU path by configuration.

2.2 ALU Path Registers

The ALU path comprises 12 data registers:

-   -   Ri0-3 Input data register 0-3 from bus    -   Rv0-3 Virtual output data register 0-3 to bus    -   Rd0-3 Internal general purpose register 0-3    -   Vi0-3 V event input 0-3 from bus    -   Ui0-3 U event input 0-3 from bus    -   Ev0-3 Virtual V event output register 0-3 to bus    -   Eu0-3 Virtual U event output register 0-3 to bus    -   Fu0-3    -   Fv0-3 Internal Flag u and v registers according to the XPP-II        PAE's event busses    -   Acc Accumulator

Eight instruction registers are implemented; each of them is 24 bit wideaccording to the opcode format.

-   -   Rc0-7 Instruction registers

Three special purpose registers are implemented:

-   -   Rlc Loop Counter, configured by CM, not accessible through        ALU-PAE itself.        -   Will be decremented according to JL opcode. Is reloaded            after value 0 is reached.    -   Rjb Jump-Back register to define the number of used entries in        Rc[0 . . . 7]. It is not accessible through ALU-PAE itself.        -   If Rpp is equal to Rjb, Rpp is immediately reset to 0. The            jump back can be bound to a condition i.e. an incoming            event. If the condition is missing, the jump back will be            delayed.    -   Rpp Program pointer

2.3 Data Duplication and Multiple Input Reads

Since Function Folding can operate in a purely data stream mode as wellas in a sequential mode (see 1.2) it is useful to support Ri reads indataflow mode (single read only) and sequential mode (multiple read).The according protocols are described below:

Each input register Ri can be configured to work in one of two differentmodes:

Dataflow Mode

This is the standard protocol of the XPP-II implementation:

A data packet is taken read from the bus if the register is empty, anACK handshake is generated. If the register is not empty ACK the data isnot latched and ACK is not generated. If the register contains data, itcan be read once. Immediately with the read access the register ismarked as empty. An empty register cannot be read.

Simplified the protocol is defined as follows:

RDY & empty → full → ACK RDY & full → notACK READ & empty → stall READ &full → read data → empty

Please note: pipeline effects are not taken into account in thisdescription and protocol.

Sequencer Mode

The input interface is according to the bus protocol definition: A datapacket is taken read from the bus if the register is empty, an ACKhandshake is generated. If the register is not empty ACK the data is notlatched and ACK is not generated.

If the register contains data it can be read multiple times during asequence. A sequence is defined from Rpp=0 to Rpp=Rjb. During this timeno new data can be written into the register. Simultaneously with thereset of Rpp to 0 the register content is cleared an new data isaccepted from the bus.

Simplified the protocol is defined as follows:

RDY & empty → full → ACK RDY & full → notACK READ & empty → stall READ &full → read data (Rpp == Rjb) → empty

Please note: pipeline effects are not taken into account in thisdescription and protocol.

2.4 Data Register and Event Handling

Data registers are directly addressed, each data register can be,individually selected. Three address opcode form is used, r_(t)←r_(s1),r_(s0). An virtual output register is selected by adding ‘o’ behind theregister. The result will be stored in r_(t) and copied to the virtualoutput register r_(v) as well according to the rule op out (r_(v),r_(t))←r_(s1), r_(s0).

Please note, accessing input and (virtual) output registers follow therules defined in chapter 2.3.

Source r_(t) Notation 000 0 Rd0 001 1 Rd1 010 2 Rd2 011 3 Rd3 100 0 Ri0101 1 Ri1 110 2 Ri2 111 3 Ri3

Target r_(t) r_(v) Notation 000 0 — Rd0 001 1 — Rd1 010 2 — Rd2 011 3 —Rd3 100 0 0 Ro0 101 1 1 Ro1 110 2 2 Ro2 111 3 3 Ro3

Events are used equal to data registers. All input and internal eventscan be addressed directly, output events are used whenever an ‘o’ isadded behind the event.

Etp ep_(t) ep_(v) Notation 000 0 — Fu0, Fv0 001 1 — Fu1, Fv1 010 2 —Fu2, Fv2 011 3 — Fu3, Fv3 100 0 0 Eou0, Eov0 101 1 1 Eou1, Eov1 110 2 2Eou2, Eov2 111 3 3 Eou3, Eov3

Es4/et4 e_(t) e_(v) Notation 0000 0 — v0 0001 1 — v1 0010 2 — v2 0011 3— v3 0100 0 0 vo0 0101 1 1 vo1 0110 2 2 vo2 0111 3 3 vo3 1000 0 — u01001 1 — u1 1010 2 — u2 1011 3 — u3 1100 0 0 uo0 1101 1 1 uo1 1110 2 2uo2 1111 3 3 uo3

2.4.1. ACCumulator Mode

To achieve low power consumption and for better supporting DSP-likealgorithms an accumulator register is available which can be addressedby just one set bit for the result register (ao) and operand register(ai).

For commutative operations always operand register 1 is replaced by ai.For non commutative operations as SUBtract operand register 1 selects,whether ai is the first or second operand. register 2 defines theaccordingly other operand.

It is to be noted that it has to be clarified whether a real ACCumulatormode makes sense or just a MAC-command should be implemented to handlethe multiply accumulate in a single command consuming two clock cycleswith an implicit hidden accumulator access.

2.4.2. Parameter Stack Mode (PSTACK)

Unused entries in the Opcode Registers Rc can operate as stack forconstants and parameters. At Rpp==0000 the Rps PStack registers pointsto Rjb+1, which means the PStack area starts immediately behind the lastentry in the Opcode register file.

To access the PStack, the FF-PAE must be in the Fast-Parameter Mode.Each read access to Ri3 is redirected to read from the PStack, whereasafter each read access the pointer incremented with one. There is nocheck for an overflow of the PStack pointer implemented; an overflow isregarded as a program bug.

(see FIG. 28 now)

2.4.3 n:1 Transitions

n:1 transitions are not supported within the busses any more.Alternatively simple writes to multiple output registers Ro and eventoutputs Eo are supported. The Virtual Output registers (Rv) and VirtualEvent (Ev) are translated to real Output registers (Ro) and real Events(Eo), whereas a virtual register can be mapped to multiple outputregisters.

To achieve this a configurable translation table is implemented for bothdata registers and event registers:

Rv Ro0 Ro1 Ro2 Ro3 Ev Eo0 Eo1 Eo2 Eo3 0 1 2 3

EXAMPLE

Rv0 mapped to Ro0, Ro1Rv1 mapped to Ro2Rv2 mapped to Ro3Rv3 unused

Rv Ro0 Ro1 Ro2 Ro3 0 1 1 0 0 1 0 0 1 0 2 0 0 0 1 3 0 0 0 0

2.4.4 Accessing Input and Output Registers (Ri/Rv) and Events (Ei/Ev)

Independently from the opcode accessing input or output registers orevents is defined as follows:

Reading an Input Register:

Register status Operation empty Wait for data full Read data andcontinue operation

Writing to an Output Register:

Register status Operation empty Write data to register full Wait untilregister is cleared and can accept new data

2.4.5. Multi-Config Mode

The Multi-Config Mode allows for selecting 1 out of maximum 4 storedconfigurations. Incoming events on Fui0,1 and Fvi0,1 select one of the 4configurations. Only one Event shall be active at a clock cycle.

The selection is done by a simple translation, each event points to aspecific memory address.

(see FIG. 29 now)

Long configurations may use more than 3 opcode by using the next codesegments as well. In this case, the according events can not be used.

(see FIG. 30 now)

2.5 Opcode Format

24 bit wide 3 address opcodes are used in a preferred embodiment:

op r_(t)←r_(a), r_(b)

Source registers can be Ri and Rd, target registers are Rv and Rd. Atypical operation targets only Rd registers. If the source register forr_(a) is Ri[x] the target register will be Rd[x].

The translation is shown is the following table:

Target Source r_(a) Rd0 Rd0 Rd1 Rd1 Rd2 Rd2 Rd3 Rd3 Rd0 Ri0 Rd1 Ri1 Rd2Ri2 Rd3 Ri3

Each operation can target a Virtual Output Register Rv by adding an outtag ‘o’ as a target identifier to the opcode:

op(r_(t), ro_(t))←r_(a), r_(b)

Data is transferred to the virtual output register and to the accordinginternal register as well:

Rv Rd Rv0 Rd0 Rv1 Rd1 Rv2 Rd2 Rv3 Rd3

2.5.1 Conditional Execution

The SKIPE command supports conditional execution. Either an event or ALUflag is tested for a specific value. Depending on the check either thenext two addresses are executed (Rpp+1) or skipped (Rpp+3). If anincoming event is checked, the program execution stops until the eventis arrived at the event port (RDY handshake set).

SKIPE supports conditional execution of any OpCode which is not largerthan two memory entries.

In SEQ-PAEs, which support CALL and RET OpCodes, also stack basedsubroutine calls are supported.

2.6 Clock

The PAE can operate at a configurable clock frequency of

-   -   1×Bus Clock    -   2×Bus Clock    -   4×Bus Clock        -   [8×Bus Clock]

2.7 The DF Path

The DataFlow path comprises the data registers Bri0 . . . 3 and Bro0 . .. 3 as well as the event register Bui/Bvi0 . . . 3 and Buo/Bvo0 . . . 3.

The main purpose of the DF path is to establish bus connections in thevertical direction. In addition the path includes a 4 stage FIFO foreach of the data and event paths.

The DF path supports numerous instructions, whereas the instruction isselected by configuration and only one of them can be performed during aconfiguration, function folding is not available.

The following instructions are implemented in the DF path:

-   -   1. ADD, SUB    -   2. NOT, AND, OR, XOR    -   3. SHL, SHR, DSHL, DSHR, DSHRU    -   4. EQ, CMP, CMPU    -   5. MERGE, DEMUX, SWAP    -   6. SORT, SORTU    -   7. ELUT

2.9 Parameter Broadcast and Update

Parameters and constants can be updated fast and synchronous using inputregister Ri3 and event input Ei7.

(see FIG. 31 now)

Depending on the update mode, data packets at the input register Ri3 arecopied subsequently into Rd3, Rd2 and Rd1 at each access of theaccording register by the PAE, if the event Ei7 is set. Afterwards allinput data at Ri3 is propagated to the output register Ro3, also the Eo7event output is set, to indicate following PAEs the occurrence of a fastparameter update, which allows to chain PAEs, together (i.e. in amulti-TAP FIR filter) and updating all parameters in the chain.

UPM1 UPM2 UPM3 Register Upmcfg = upmcfg = upmcfg = access Ei7 0100 10001100 — 0 — — — read Rd3 1 Ri3 -> Rd3 Ri3 -> Rd3 Ri3 -> Rd3 read Rd2 1Ri3 -> Ro3 Ri3 -> Rd2 Ri3 -> Rd2 1 -> Eo7 read 1 Ri3 -> Ro3 Ri3 -> Ro3Ri3 -> Rd1 Rd1 1 -> Eo7 1 -> Eo7 — 1 Ri3 -> Ro3 Ri3 -> Ro3 Ri3 -> Ro3 1-> Eo7 1 -> Eo7 1 -> Eo7

Also the OpCode UPDATE updates all registers subsequently if Ei7 is set,depending on the Update Parameter Mode (upmcfg=nn10).

Also the register update can be configured to occur whenever Rpp==0 andEi7 is set by upmcfg=nn01.

In both cases nn indicates the number of registers to be updated (1-3).

Ei7 must be 0 for at least one clock cycle to indicate the end of arunning parameter update and the start of a new update.

3 Input Output Address Generators (IOAG)

The IOAGs are located in the RAM-PAEs and share the same registers tothe busses. An IOAG comprises 3 counters with forwarded carries. Thevalues of the counters and an immediate address input from the array areadded to generate the address. One counter offers reverse carrycapabilities.

3.1 Addressing Modes

Several addressing modes are supported by the IOAG to support typicalDSP-like addressing:

Mode Description Immediate Address generated by the PAE array xDcounting Multidimensional addressing using IOAG internal counters xDmeans 1D, 2D, 3D xD circular Multidimensional addressing using IOAGinternal counters, after overflow counters- reload with base address xDplus immediate xD plus a value from the PAE array Stack decrement after“push” operations increment after “read” operations Reverse carryReverse carry for applications such as FFT

3.1.1 Immediate Addressing

The address is generated in the array and directly fed through the adderto the address output. All counters are disabled and set to 0.

3.1.2 xD Counting

Counters are enabled depending on the required dimension (x-dimensionsrequire x counters). For each counter a base address and the step widthas well as the maximum address are configured. Each carry is forwardedto the next higher and enabled counter; after carry the counter isreloaded with the start address.

A carry at the highest enabled counter generates an event, countingstops.

3.1.3 xD Circular

The operation is exactly the same as for xD counting, with thedifference that a carry at the highest enabled counter generates anevent, all counters are reloaded to their base address and continuecounting.

3.1.4 Stack

One counter (CNT1) is used to decrement after data writes and incrementafter data reads. The base value of the counter can either be configured(base address) or loaded by the PAE array.

3.1.5 Reverse Carry

Typically carry is forwarded from LSB to MSB. Forwarding the carry tothe opposite direction (reverse carry) allows generating addresspatterns which are very well suited for applications like FFT and thelike. The carry is discarded at MSB.

For using reverse carry a value larger than LSB must be added to theactual value to count, wherefore the STEP register is used.

Example Base=0h Step=1000b

Step Counter Value 1 B0 . . . 00000 2 B0 . . . 01000 3 B0 . . . 00100 4B0 . . . 01100 5 B0 . . . 00010 . . . . . . 16  B0 . . . 01111 17  B0 .. . 00000

The counter is implemented to allow reverse carry at least for STEPvalues of −2, −1, +1, +2.

4. ALU/RAM Sequencers—SEQ-PAEs

Each ALU-PAE at the left or right edge of the array can be closelycoupled to the neighbouring RAM-PAEs as an IP option, thus allowing forconfigure a sequencer. For compatibility reasons, the data and opcodewidth of the sequencer is 16 bits.

(see FIG. 19 now)

The ALU-PAEs can operate exactly as array internal ALU-PAEs but haveseveral extensions. Operation is Sequencer mode the register file is 8data registers wide, Fu and Fv flags are, used as carry, sign, null,overflow and parity ALU flag word 112.

Event Processor Registers Registers FF-Mode SEQ-Mode Fu0 carry Fu1 signFu2 null Fu3 overflow Fv0 parity

The address width is accordingly 16 bit. However since the RAM-PAE sizeis limited it is segmented into 16 segments. Those segments are used forcode, data and stack 3300 and must be individually preloaded by thecompiler.

4 Segment Registers Point to the Specific Segments:

CodeBank Points to the actual code segment DataBank Points to the actualdata segment StackBank Points to the actual stack segment AuxiliaryBankPoints to any Segment (but code), allowing copy operations betweensegments(see FIG. 32 now)

The compiler has to take care that necessary data segments are preloadedand available. For cost reasons there is no automatic TLB installed.

Also segments have to be physically direct addressed due to the absenceof TLBs. This means that the compiler has to implement range checkingfunctions for according addresses.

Code segments behave accordingly to data segments. The compiler has topreload them before execution jumps into them. Also jumps are physicallydirect addressed, due to the absence of TLBs again.

A relocation of any segments is not possible; the mapping is fixed bythe compiler.

The memory layout is shown in FIG. 33 now. A simple check mechanism isimplemented to validate or invalidate memory segments.

At least the CodeBank (CB) and StackBank (SB) must be set. The firstCodeBank must start at location 0000 h. For all other banks 0000 h is anillegal entry. Loading segments to the memory validates them,accordingly flushing invalidates them.

Memory banks 3500 are updates in terms of loaded or flushed in thebackground by a DMA engine controlled by the following opcodes

LOADDSEG Loads and validates a data/auxiliary/stack bank STOREDSEGStores and invalidates a data/auxiliary/stack bank LOADCSEG Loads andvalidates a code bank

The address generators 3502 in the IOAG interfaces can be reused as DMAengine.

Memory Banks can be Specifically Validated or Invalidated as Follows:

VALIDATESSEG Validates a bank INVALIDATESEG Invalidates a bank

The bank pointers are added to the address of any memory access. Sincethe address pointer can be larger than the 6 bits addressing a 64 linerange, segment boarders are not “sharp”, which means, can be crossedwithout any limitation. However the programmer or compiler has to takecare that no damage occurs while crossing them. If an invalid segment isreached a flag or trap is generated indicating the fault, eventuallyjust wait states are inserted if a segment preload is running already inthe background.

(see FIG. 34 now)

Alternatively a more advanced valid checking scheme can be implementedas shown in FIG. 35 now.

In difference to PAEs which require 24-bit instructions sequencers use16-bit instructions only. To use the same instruction set and to keepthe decoders simple, just the last 8 bits are discarded in sequencermode.

4.1 IOAGs

IOAGs may comprise a 4-8 stage data output buffer to balance externallatency and allow reading the same data address directly after the datahas been written, regardless of external bus or memory latencies (up tothe number of buffer stages).

In the following, a number of OpCodes and their meanings is suggested:

In the following, an example for the use of function folding is given:

Function Folding and Fast Parameter Update Example FIR Ri0=x Ri1=y

3-Folded FIR Using Acc Fast Parameter Update for Registers Rd1, Rd2, Rd3Example 1 UPM3, Updates Parameters with Each Access to Rd3, 2, 1 (if Ei7is Set)

upmcfg=1100# stage 1

-   -   mul acc, Ri0, Rd3;    -   add Rd0, acc, Ri1;        # stage 2    -   mul acc, Ri0, Rd2;    -   add Rd0, acc, Rd0;        # stage 3    -   mul acc, Ri0, Rd1;    -   add Ro1, acc, Rd3;    -   write Ro0, Ri0;

Alternative using MAC opcode, parameter pop and looping

-   -   read Rd0, Ri1;        1 h, 1 t[3]: mac Rd0, Ri0, pop;    -   write Ro1, Rd0;    -   write Ro0, Ri0;

Example 2 UPM3, Uses Command UPDATE for Parameter Update

upmcfg=1110# stage 1

-   -   mul acc, Ri0, Rd3;    -   add Rd0, acc, Ri1;        # stage 2    -   mul acc, Ri0, Rd2;    -   add Rd0, acc, Rd0;        # stage 3    -   mul acc, Ri0, Rd1;    -   add Ro1, acc, Rd3;    -   write Ro0, Ri0;    -   update 3

Example 3 UPM3, Updates Parameters at Rpp==0

upmcfg=1101# stage 1

-   -   mul acc, Ri0, Rd3;    -   add Rd0, acc, Ri1;        # stage 2    -   mul acc, Ri0, Rd2;    -   add Rd0, acc, Rd0;        # stage 3    -   mul acc, Ri0, Rd1;    -   add Ro1, acc, Rd3;    -   write Ro0, Ri0;

In the above, an improved data processor array has been described.Although only in some instances, it has been pointed out that referenceto a certain number of registers, bit width etc. is for explanationonly, it is to be understood that this also holds where such referenceis not found.

If the array is to be very large or in case a real time process is runwhere two different fragments of an array unknown at compile time haveto communicate with each other so as to enable data processing, it isadvantageous to improve the performance by ensuring that a communicationpath can be set up. Several suggestions have been made already, e.g.Lee-Routing and/or the method described in PACT 7. It is to beunderstood that the following part of an improved array design mightresult in an improved circuitry for certain applications but that it isnot deemed absolutely and inevitably necessary to implement it with e.g.a function fold PAE. Rather, the other suggestions for improvement willresult in significant improvements on their own as will be understood bythe average skilled person.

Routing Improvement

The suggested improvement described hereinafter concerns the staticrouting network for reconfigurable array architectures. Hereby thisstatic network is enhanced by implementing additional logic to adaptiveruntime routing.

FIG. 1 depicts a cut-out of a reconfigurable array with a set offunctional units (FU). Each functional unit encloses one routing unit(RU) and additional functional modules (FMs). The enclosed functionalmodules are used to manipulate data and characterize the type of the FU.The RU contains an interconnect matrix which is able to route each inputport to any desirable output ports. All FUs are connected throughpoint-to-point links whereas each is composed of two half-duplex linksand able to transport the data in both directions at the same time.

The routing technique described in this document is instruction basedwhich means that each routing process must be started by an instruction.If the user wants to establish a routing between two cells, he has tobring a specific instruction into the source cell. The hardware withinthe array calculates based on the instruction fields values the desiredrouting direction and establishes the logic stream. The routing processhappens stepwise from one functional unit to another whereby each celldecides which direction should be taken next. On the way to anestablished route we defined three valuable states of the routingresources. The first state is the physical route or link. This meansthat the resources of this route are not used and available to routingprocesses. The second state is named temporal route or link. This statedescribes the temporarily not available link, which means that this linkis in use for routing purposes but the mentioned routing is notconfirmed yet. The problem here is that this route can be confirmed inthe future or released if the successor cells are able to realise thedesired routing. The last state is the logical route or link. This staterepresents an established route on the array which is able to transportcalculation data.

This routing technique uses coordinates on the array to calculationroutings. Each FU possesses unique coordinate's and on the basis of thisinformation it is able to determine the routing direction to eachdesired cell Within the array. This concept is the basis for theadaptive runtime routing described in this document. The needed controllogic for adaptive routing is implemented within the routing unit,especially within the routing controller which controls the interconnectmatrix at runtime. Therefore the routing controller is able to analyzethe incoming data of all input ports of the concerned FU and come to adecision what to do next.

Routing Establishment

For the purpose of incoming data analyzing and data buffering each inputport owns so called in-registers (InReg). Additional to those standardregisters there are InReg-controllers implemented (InRegCtrl). Thosefinite state machines (FSMs) have the job to store the actual state ofthe input links and in dependency of the actual state to trigger routingrequests or release not required routings. To fulfill its job eachInRegCtrl is connected to an in-controller (InCtrl) which is implementedexactly once per FU. Important requirement for requesting of newroutings is that the mentioned input resource (InReg, InRegCtrl) are notused and so in the state of physical link.

InCtrl gets requests of all InRegCtrls all over the time and forwardsone request after another to the routing controller (RoutCtrl). Theselection which InRegCtrl should be served first is dependant on therouting priority of the input link and/or which input link was servedlast. Based on the coordinate information of the target cell and thecoordinates of the actual FU the RoutCtrl calculates the forwarddirection for the requested input link. Thereby the RoutCtrl takes intoaccount additional parameters like optimum bit (will be describedlater), the network utilisation towards the desired direction, etc.

If the direction calculation within the RoutCtrl was successful theRoutCtrl forwards the request with additional information about theoutput port to the interconnect matrix, which connects the input portwith calculated output port. If this is done the RoutCtrl signals thesuccessful routing operation to InCtrl. Because the actual reachedrouting state is not final it is necessary to store the actual state.This happens within the queue-request-registerfile (QueueRRF). Thereforethe InCtrl is directly connected to the QueueRRF and is able to storethe desired information. At this point the related input and outputlinks reach the temporal link state and are temporarily not availablefor other routing processes.

Due the fact that the QueueRRF is able to store more than one routingentry, the InCtrl is able to hold multiple routing processes at the sametime. But for the purpose of high hardware area consumption thedirection calculation is realized once within the RoutCtrl.

The established temporal routing stays stored within the QueueRRF tillthe point the successor cell acknowledges the routing. In this case theInCtrl clear the according entry in the QueueRRF and signals thesuccessful routing to the InCtrl. The InRegCtrl changes into the statelogical route and signal the predecessor cell the successfully finishedrouting process.

The other case can happen if the successor cell is not able to establishthe desired route. In this case the InCtrl forwards a new request to theRoutCtrl based on the QueueRRF-entry. This request leads to new routingsuggestion which will be stored within the QueueRRF.

If all available and expedient directions are checked and routing trialsfailed the InCtrl signals to InRegCtrl the failed routing. The InCtrlsignals the same routing miss to the predecessor cell and finishes therouting process in the current cell.

Within the routing process there are two exceptions how the routing unitestablishes a desired routing. Those exceptions affect the source andthe target cell. The exception in both cases is that as well the sourcecell as the target cell do not need to route the started/ending routingthrough the interconnect matrix. To connect the FMs to the output linksof cells simple multiplexers are used. Those multiplexers areimplemented after the interconnect matrix and have to be switchedexplicitly. This happens after the routing process is finished. Theexception lies in the finishing state. Here the InRegCtrl doesn't haveto acknowledge the successful routing the predecessor it just has toconsume the actual routing instruction in the InReg instead. Thishappens after the InCtrl signals the successful routing. Additionallythe InReg switches the output multiplexer associated to the output portof the FM and finishes the routing establishment. The information neededthe switch the right output multiplexer gets the InCtrl from theRoutCtrl.

Otherwise if the routing fails the InCtrl asserts cell specificinterrupt line and signals the failure to the system.

The second exception concerns the target routing cell. Here it isimportant to connect the new route with the input ports of the local FM.Therefore simple multiplexers are used which are implemented before theinterconnect matrix. If an ongoing routing process reaches the targetcell the InCtrl identifies the target achievement and switches theassociated input multiplexer to forward the incoming data to the inputport of the FM. This is the point where, the successful routeestablishment signal is generated by the InRegCtrl after InCtrl signalsthe success. Here the InRegctrl has the last job to finish the routingprocess by deleting the routing instruction and going to logical state.

Releasing Established Routing

For releasing of the logically established routings we introducedspecial instructions, so called end packets. The only purpose of thoseinstructions is the route-dissolving by inject the necessary end packetinto the logic established routing. There are two ways how the routingscan be released. The first possibility is the global releasing. Thismeans that all routes which are following the route where the end packetis injected will be released. This function is useful to delete wholeconfigurations with one single instruction. For this purpose it isimportant that the FMs are able to forward the end packet unalteredthrough the internal datapaths.

The second way for route releasing is the local route releasing. Here itis possible to release single established routes between output andinput ports of FMs. The end packets are not propagated through the FMs.In this case the end packet will be consumed by the last InRegCtrl.

The internal RU communication is similar to the routing process. If theInRegCtrl determines incoming end packet and the InRegctrl is in thelogic route state, the InRegCtrl forwards the route release request tothe InCtrl. The InCtrl clears the entries either within the interconnectmatrix or within the input multiplexers registers or within the outputmultiplexer registers. Meanwhile the InRegCtrl consumes (in case of thelocal end packet and last cell in the chain) the instruction and goes tothe idle state. If the end packet was a global instruction the InRegCtrlforwards always the end packet to the successor.

Additional Features

For the purpose of priority control, we introduced a priority system toinfluence the order in which the RU serves the incoming routingrequests. Therefore the instructions contain priority fields whichdescribe the priority level. Higher values in this field result inhigher priority and will be preferred by the RU during theruntime-routing. The priority field has direct influence on theselection of the incoming routing requests from the InRegCtrls toInCtrl.

Some inner configuration communication streams require strictly definedlatency to reach the desired performance. Therefore it is very importantto keep the maximum register chain length. To decrease the latency ofthe routed streams its is necessary to ensure that the array chosealways the best routing between source and target, but this requirementmay lead to not routable streams if this feature will be alwaysrequired. To ease this problem we introduced a special bit within therouting instruction, so called optimum bit (OptBit). This bit has to beactivated if the optimum routing is definitely required. In this casethe array tries to reach this requirement and delivers an interrupt iffails.

The alternative to reach the required latency is the speed path counter.This counter gives the possibility to bypass a specific number ofregisters before buffering again. Therefore we defined a reference valueand the counter value. Both numbers are stored within the instructionfield. Each passed cell respective the RU compares the counter value andthe reference value. If both values are equal then the actual cellbuffers the stream and resets the counter. If the counter is smallerthan the reference value the current buffer will be bypassed and thecounter incremented by one. In this way it is possible to bypass anumber of buffers which equals exactly to reference value.

Multi-Grained Communication Links

In addition to the coarse-grained point-to-point links we introducedmore flexible multi-grained point-to-point links. Hereby one singlepoint-to-point link connects two neighbor cells respective the RUswithin those cells. One coarse-grained link consists of a set of wires,e.g. 32 wires for one 32 link, and additionally protocol signals. Thewhole vector is handled by a single set of control signals which makesthis communication resource not usable for multi-grained communication.

To reach this requirement we divided the whole 32 bit vector into singlestrips, e.g. with groups of 8 times 1 bit strips and 3 times 8 bitstrips. Each strip obtained separate control signals and is able tooperate independently from other strips.

The idea behind this division is to combine those strips to logicalmulti-grained sub-links. If you have one multi-grained link you can usethe whole vector as one interrelated 32 bit vector or split the wholevector into sub-channels. In this configuration each strip can be onesingle sub-channel or a group of strips can be gathered to a singlesub-channel of desired bit-width. You just have—in respect of hardwarecosts—to consider that one sub-channel has to fit into one multi-grainedlink.

Multi-Grained Routing

In order to route multi-grained channels its necessary to use the coarsegrained links to support the routing process. The idea is to route twolinks in parallel, one coarse-grained link to support multi-grainedrouting and one multi-grained link, which will contain the finalmulti-grained stream. Therefore we defined a two packet routinginstruction with needed data fields. The first instruction packetcontains—compared to coarse-grained routing instruction—additional bitmask to specify used multi-grained sub-links and multi-grained link IDto identify the associated multi-grained link. The other features likedescribed above—optimum bit, speed path, priority routing—are support inthis routing mode as well. The routing process within the RU isperformed similar to the coarse-grained routing.

The first packet which arrives in a cell is analyzed by the InRegCtrland a request is generated and forwarded to the InCtrl. InCtrl forwardsthe request to the RoutCtrl and wait for the acknowledgement. IfRoutCtrl finds one possible routing direction, the InCtrl gets thesuccessful acknowledgement and the temporal routing will be establishedby the RoutCtrl. Next, the actual job will be stored within the QueueRRPand the InCtrl waits for the acknowledgement from the successor cell. IfRoutCtrl is not able to find a possible routing, the InCtrl getsnegative acknowledgement and which will be forwarded to the associatedInRegCtrl, which generates the route unable signal to the predecessorcell and quits the routing process within this cell.

If the successor cell signals successful routing, the InRegCtrl clearsthe related entry in the QueueRRP and finishes the routing. If thesuccessor cell is not able to establish a rout to the destination cell,it generates negative acknowledgement signal. Hereupon, the InCtlrstarts new request to the RoutCtrl and handle the responses as describedabove.

The difference between the coarse-grained routing and multi-grainedrouting lies in the handling of the multi-grained interconnect matrix.Each strip of a multi-grained link is handled separately. The RoutCtrlforwards the switch request to the strip matcher. Strip matcher has thejob to analyze the input strips and to match them to the output linkaccording to already used strips. What strip matcher is doing is to mapthe problem of strip matching into the time domain and switches theneeded switchboxes for each strip separately one after another.

Routing Packet for Coarse-Grained Streams:

3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 2 1 09 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ValueComments 32  1 instruction-packet 31 30 00 ID: Routing-packet forcoarse-grained streams 29 28 XX Priority-level: higher value results inhigher priority 27 26 XX Speed path: Reference value 25 24 XX Speedpath: Counter 23 X Optimum bit (OptBit): 1 enabled; 0 disabled 22 . . .19 XXXX FM output address within the source cell 18 . . . 15 XXXX FMinput address within the destination cell 14 X Use fine-grained links: 1= yes, 0 = no 13 . . . 8 Reserved 7 . . . 4 X . . . X Destination cellcoordinates: x-coordinate 3 . . . 0 X . . . X Destination cellcoordinates: y-coordinate

Routing Instruction for Multi-Grained Streams (First Packet):

3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 2 1 09 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ValueComments 32  1 Instructions-packet 31 30 01 ID: Routing-instructionmulti-grained streams (first packet) 29 28 XX Priority-level: highervalue results in higher priority 27 26 XX Speed path: Reference value 2524 XX Speed path: Counter 23 X Optimum bit (OptBit): 1 enabled; 0disabled 22 — Reserved 21 . . . 19 XXX ID of the input stream of themulti-grained link 18 . . . 16 XXX 8 bit strips mask: 1 = selected; 0 =not selected 15 . . . 8 X. . . X 1 bit strips mask: 1 = selected; 0 =not selected 7 . . . 4 XXXX Destination cell coordinates: x-coordinate 30 XXXX Destination cell coordinates: y-coordinate

Second Packet of the Routing Instruction for Multi-Grained Streams:

3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 2 1 09 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ValueComments 32  1 Instructions-packet 31 . . . 30 10 ID:Routing-instruction multi-grained streams (first packet) 29 28 XReserved 27 . . . 25 XXX Destination cell 8 bit strips mask: 1 =selected; 0 = not selected 24 . . . 17 X . . . X Destination cell 1 bitstrips mask: 1 = selected; 0 = not selected 16 . . . 14 XXXMulti-grained FM input port address of the destination cell 13 . . . 11XXX Source cell 8 bit strips mask: 1 = selected; 0 = not selected 10 . .. 3 X . . . X Source cell 1 bit strips mask: 1 = selected; 0 = notselected 2 . . . 0 XXX Multi-grained FM output port address of thesource cell

End Packet Instruction:

3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 2 1 09 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ValueComments 32  1 Instruktions-Paket 31 . . . 30 11 ID: End packet forlogical stream releasing 29 X Coarse-/fine-grained releasing: 1coarse-grained, 0 fine-grained 28 X Local/global route release process:1 = local, 0 = global 27 . . . 23 - . . . - Reserved 22 . . . 19 XXXX FMoutput address within the source cell 18 . . . 14 - . . . - Reserved 13. . . 11 XXX Source cell 8 bit strips mask: 1 = selected; 0 = notselected 10 . . . 3 X . . . X Source cell 1 bit strips mask: 1 =selected; 0 = not selected 2 . . . 0 XXX Multi-grained FM output portaddress of the source cell

Data Packet:

3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 2 1 09 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 ValueComments 32 0 Data packet 31 . . . 0 X . . . X Application data

FIGS. 36 to 44 relate to an improved way of routing.

Using Function Folding to Improve Silicon Efficiency of ReconfigurableArithmetic Arrays

This section presents Function Folding, a design principle to improvethe silicon efficiency of reconfigurable arithmetic (coarse-grain)arrays. Though highly parallel implementations of DSP algorithms havebeen demonstrated on these arrays, the overall silicon efficiency ofcurrent devices is limited by both the large numbers of ALUs required inthe array and by the only moderate speeds which are achieved. Theoperating frequencies are mainly limited by the requirements ofnon-local routing connections. We present a novel approach to overcomethese limitations; In Function Folding, a small number of distinctoperators belonging to the same configuration are folded onto the sameALU, i.e. executed sequentially on one processing element. The ALU iscontrolled by a program repetitively executing the same instructionsequence. Data only required locally is stored in a local register file.This sequential approach uses the individual ALU resources moreefficiently, while all processing elements of the array work in parallelas in current devices. Additionally, the ALUs and local registers can beclocked with a higher frequency than the (non-local) routingconnections. Overall, a higher computational density than in currentdevices results.

1 INTRODUCTION

Field-Programmable Gate Arrays (FPGAs) are used as a flexible,programmable alternative to Application Specific Integrated Circuits(ASICs) for bit-oriented applications. They combine low NRE costs withfast time-to-market. See R. Hartenstein, “A Decade of ReconfigurableComputing: A Visionary Retrospective,” In Proc. Design, Automation andTest in Europe, 2001 (“Hartenstein”). Similarly, reconfigurablearithmetic arrays—based on coarse-grain ALUs rather than bit-levellookup tables—are such an alternative for word-level, arithmeticapplications. There are several research projects (e.g., Rapid (see D.C. Cronquist et al., “Architecture design of reconfigurable pipelineddatapaths,” In Pros. 20th Anniversary Conference on Advanced Research inVLSI, Atlanta, Ga., March 1999), KressArray (see Hartenstein and see R.Hartenstein et al., “A New FPGA architecture for word-orienteddatapaths, In Proc. Field-Programmable Logic, 4th InternationalWorkshop, Springer-Verlag, September 1994 (“Hartenstein et al.”))) aswell as commercial developments (e.g., PACT XPP Technologies (see V.Baumgarte et al., “PACT XPP—A Self-Reconfigurable Data ProcessingArchitecture,” The Journal of Supercomputing, 26(2), September 2003(“Baumgarte et al.”), Morphotech (see M. H. Lee et al., “Design andImplementation of the MorphoSys Reconfigurable Computing Processor,”Journal of VLSI and Signal Processing Systems for Signal, Image andVideo Technology, March 2000 (“Lee et al.”)), Elixent (see T.Stansfield, “Using Multiplexers for Control and Data in D-Fabrix, InField Programmable Logic and Applications, LNCS 2778, pp. 416-425,Springer, 2003)) in this area. However, these architectures have notseen widespread use yet though highly parallel implementations of DSPalgorithms have been demonstrated on them. One apparent reason for thisis the limited silicon efficiency of current devices, resulting in botha large number of ALUs required in the array and in only moderate speedsbeing achieved. The operating frequencies are mainly limited by therequirements of non-local routing connections.

We present an extension of PACT XPP Technologies' eXtreme ProcessingPlatform (XPP) (see Baumgarte et al.) which overcomes these limitations:Rather than executing a fixed operation on an ALU for the entireduration of a configuration, a small number of distinct operatorsbelonging to the same configuration are folded onto the same ALU, i.e.executed sequentially on the same processing element (PE). The ALU iscontrolled by a program repetitively executing the same instructionsequence. Data only required locally is stored in a local register file.This sequential approach uses the individual ALU resources moreefficiently, while all processing elements of the array work in parallelas in current devices. Since external data transfers are not required inevery PE clock cycle, the ALUs and local registers can be clocked with ahigher frequency than the (non-local) routing connections. This ALUoverclocking technique is also justified by the continuous trend tohigher integration densities: New technology generations provide smallerand smaller transistors, but the wires have higher relative capacitieswhich make the busses slower and more power-consuming.

Despite these significant architectural changes, existing XPP programscan be automatically mapped to this extended architecture. Overall, ahigher computational density than in current devices results.

The remainder of this section is organized as follows:

First, we describe the current PACT XPP architecture. Next, Section 3describes the functionality and hardware design of the new FunctionFolding PE, Section 4 elaborates the application mapping methods, andSection 5 presents preliminary results. Finally, our approach iscompared to related work, conclusions are drawn, and future work isoutlined.

2 XPP ARCHITECTURE OVERVIEW

The current XPP architecture (see Baumgarte et al.) is based on a 2-Darray of coarse-grain, adaptive processing elements (PEs), internalmemories, and interconnection resources. A 24-bit prototype chip with 64ALUs and 16 internal memories was built by PACT XPP Technologies. Adevelopment board for this XPP64A chip is available.

PACT also provides a complete development tool suite consisting of aplacer and router, a simulator, and a visualizer. The tools use theproprietary Native Mapping Language (NML), a structural language withreconfiguration primitives. A C frontend is provided as well.

2.1 Array Structure

FIG. 45 shows the basic structure of a simple XPP core. Fordemonstration purposes, it contains only 9 PEs 4502 and 6 internal RAMs4504. The core comprises a 3×3 square of PEs in the center and onecolumn of independent internal memories on each side. There are two I/Ounits 4506 which can either be configured as ports for streaming data oras interfaces for external RAM access. The core of a PE is an ALU whichperforms common arithmetic and logical operations, comparisons, andspecial operations such as counters. In each configuration, each PEperforms one dedicated operation. Each line in the figure represents aset of segmented busses which can be configured to connect the output ofa PE with other PEs' inputs. The array is attached to a ConfigurationManager (CM) 4508 responsible for the runtime management ofconfigurations, i.e. for downloading configuration data from externalmemory into the configurable resources of the array. Besides a finitestate machine 4510, the CM has cache memory 4512 for storing orpre-fetching configuration data.

2.2 Data and Event Synchronization

The interconnection resources consist of two independent sets of busses:data busses (with a device specific bit-width) and one-bit wide eventbusses. The XPP busses are not just wires to connect logic: aready/acknowledge protocol implemented in hardware synchronizes the dataand events processed by the PEs. Hence a PE operation is performed assoon as all necessary input values are available and the previous resulthas been consumed. Thus it is possible to map a dataflow graph directlyto the array, and to pipeline input data streams through it. No data islost even during pipeline stalls. Special dataflow operations for streammerging, multiplexing etc. are provided as well.

2.3 Configuration

Compared to FPGAs, XPP cores can be configured rapidly due to theircoarse-grain nature: Only opcodes and connections have to be set.Furthermore, only those array objects actually used need to beconfigured.

The configuration time can be reduced by prefetching mechanisms: duringthe loading of a configuration onto the array another configuration canbe loaded to the CM cache. Thus it must not be loaded from externalmemory when it is requested. The same is true if a configuration hasbeen used before and its configuration data is still in the CM cache.

3 FUNCTION FOLDING PE

We now describe the functionality and hardware design of an extended XPPPE, the Function Folding Processing Element.

3.1 Function Folding Example

Let us first consider a simple example: An address adr is computed froma constant offset offs and coordinates x and y as follows:adr=offs+x+256*y. In an XPP implementation based on simple PEs as shownin FIG. 45, this computation is normally directly mapped to the dataflowgraph in FIG. 47A. Each adder and multiplier is mapped to its own ALU.Therefore a new address can be computed every cycle. However, asmentioned in Section 1, the operating frequency is limited by the busconnections, not by the ALU itself.

For a higher silicon efficiency, i.e. for more operations per squaremillimeter and second, the ALUs have to be clocked faster. This could beachieved by more pipeline registers in the busses. But theyunfortunately increase the chip area and power consumption and reducethe throughput if the dataflow graph contains cycles. In our approach,we rather operate the busses at a moderate frequency (as in the currentXPP cores) and increase the ALU's clock rate locally inside a PE. Thisn-fold overclocking allows to schedule n ALU operations in one bus cycle(for a small number n). We call these groups of operations clusters. Thesignificant reduction in the number of PEs required justifies thehardware overhead incurred. While sticking to the successful paradigm ofreconfigurable “computing in space”, this locally sequential approachoptimizes the usage of the ALU resources.

By allowing different overclocking factors in the same device (e.g. n=2and n=4), different local time-space tradeoffs are possible. For n=4, inour example, all operations in the dataflow graph can be clustered, i.e.executed on the same ALU, even if the multiplication requires twocycles. For n=2, only the two adders can be clustered. This results intwice the area, but also doubles the throughput compared to n=4.

Apart from a program controller executing the n instructionsrepetitively, a small internal register file to feed intermediateresults back to the ALU inputs is required in the PE. This localfeedback loop allows implementing dataflow graphs with cycles containingup to n operators without reducing the overall throughput.

3.2 Hardware Design

The hardware design sketched in FIG. 46 performs Function Folding asdescribed above. As the simple PEs in FIG. 45, the new PE communicateswith the interconnect network via data and event input and output portswhich follow the ready/acknowledge protocol. The ports also synchronizethe fast internal PE clock with the n-times slower bus clock. Input datais stable during the entire bus clock cycle, i.e. can be sampled in anyof the internal PE clock cycles. And output data is copied to the busregisters at the beginning of a bus cycle. A Function Folding PErequires more ports than a simple PE since it executes an entire clusterof operations. But it does not require n-times more ports than thesimple PE since the number of external connections is often quitelimited due to constant inputs (which can be loaded to internalregisters at configuration time) and local connections within a cluster.A good clustering algorithm minimizes the number of externalconnections. As illustrated by the dotted box around the operators inFIG. 47B, only two input ports and one output port are required for theexample cluster for n=4.

In detail, the PE in FIG. 46 works as follows: A small program counter(PC) 4602 repeatedly iterates through the configured instructions in theinstruction store 4604. In each PE cycle it selects the ALU opcode andcontrols the multiplexors selecting the ALU inputs. Either an input portor an entry of the internal register file 4606 can be used. The ALUoutputs can be written back to the internal register file or to anoutput port or to both. The entire design is kept as simple and small aspossible to just support function folding. No other control structuresare possible. Both the number of input and output ports and the numberof internal registers will be about n. Therefore we can choose a veryfast implementation of the register file just using registers andmultiplexors. Given the small number of ports and registers, the entirefetch/execute/store process can be performed in one cycle. The onlyexception is the multiplier operation which takes two cycles. Thecontroller (FSM) 4608 stalls the program execution if an external inputis not available or if an external output port is full due to adownstream pipeline stall. Note that event ports and registers areomitted in FIG. 46 for clarity. Events can be used and stored internallyand externally like data.

Returning to FIG. 47B, we can now present the simple PE program for theaddress generation cluster. The mapping of connections to ports andregisters is indicated in the figure. We assume that registers r1 and r2have been initialized with the constant values offs and 256,respectively, at configuration time. The following assembler code,executed repetitively, describes the cluster:

-   -   add r3<-r1, i1    -   mul r4<-r2, i2    -   add o1<-r3, r4

4 APPLICATION MAPPING

FIG. 48 shows the tool flow of the extended XPP architecture. It is verysimilar to the current tool flow implemented in the xmap program (seeBaumgarte et al.). Only the phases represented by the shaded boxes areadded. The following phases already exist in the current XPP tool flow:

-   -   Cfrontend (optional): Generates structural NML code (cf.        Section 2) from a subset of standard C.    -   NML parser: Parses the input NML file and maps it to XPP        operators.    -   Place and Route: Places the PEs (i.e. operators in the current        architecture) on the XPP array and routes the connections.    -   Binary Generation: Generates an XBIN binary file.

For Function Folding, an additional Operator Clustering phase isrequired which defines the operators mapped to one PE. Though theclusters could be defined manually by annotations in the NML file, anautomatic clustering algorithm is required to simplify programming, touse the C frontend, and to map existing NML code. It is described in thenext section. Furthermore, PE program code needs to be generated foreach cluster as described in Section 4.2. Obviously the Place and Routeand Binary Generation phases have to be adapted, too.

4.1 Operator Clustering

The operator clustering problem for Function Folding PEs is similar tothe graph covering problems encountered in code generators forconventional processors and module mapping for FPGAs, e.g. T. J.Callahan et al., “Fast Module Mapping and Placement for Datapaths inFPGAs,” In Proc. FPGA '98, Monterrey, Calif., 1998 (“Callahan et al.”).Therefore we investigated these algorithms first. The efficientdynamic-programming algorithm used in Callahan et al. and similarapproaches is actually a tree-covering algorithm. It generates optimalcoverings for operator trees. But it cannot handle arbitrary dataflowgraphs. Hence a preprocessing phase which removes feedback cycles andfanout edges from the original graph is required. The result is a forestof trees which can be covered efficiently. However, the optimal treecovering results are not optimal for the original dataflow graph.

Now consider the operator clustering problem at hand: We need to find asolution with the minimal number of clusters which conforms to therestrictions of the Function Folding PEs, i.e. the over-clocking factorn, and the number of ports and internal registers. Additionally, cyclesshould be processed within a cluster whenever possible (to avoid reducedthroughput caused by external routing delays), and the number ofexternal connections should be minimized. Unfortunately these qualitycriteria are not visible in the output of the tree coveringpreprocessing phase, i.e. after the removal of cycles and fanout edges.Hence we do not apply tree covering for operator clustering.

Instead, we developed an algorithm operating on the original graph. Toreduce the complexity, we only consider clustering operators which areconnected since only these clusters use internal registers and reducethe number of external ports. In an additional postprocessing phase,unconnected clusters can be merged later if they are placed next to eachother.

In the first algorithm phase, all connected clusters are explicitlygenerated. Note that the number of possible unconnected clusters wouldbe exponential in the number of operators.

In the second phase, the optimal combination of clusters covering theentire input graph has to be determined. Unfortunately the number of allpossible combinations of clusters is exponential. Hence it cannot besearched exhaustively. Instead, the main loop of the algorithm operateson an increasing subset of the operators, generating and storing anoptimal clustering of the subset, until the optimal clustering of theentire operator graph has been computed. The algorithm exploits the factthat partial optimal solutions are contained in the complete optimalsolution. In this way we do not need to compute optimal clusterings forall subsets. Because the optimal clustering of a new subset depends onother subsets which might not have been computed before, some recursivecalls which may lead to an exponential runtime are required. However, wefound that the runtime is in the range of a few minutes for anoverclocking factor n<=4 and for an operator number k<50. For largerproblem sizes we tested the following heuristics:

-   -   Remove large feedback cycles (with more than n operators) from        the graph. Then small cycles are still executed within a cluster        and only a few possible clusters are excluded, but the number of        recursive calls is largely reduced.    -   Do not compute the best solution in recursive calls, but only        the first clustering of the subset which is computed. By        applying larger clusters before smaller ones, the algorithm        computes a nearly optimal solution anyway.

With these extensions we could quickly cluster realistic dataflow graphswith up to 150 operators. For the cases we tested, the heuristicsproduced clusterings which were very near or equal to the optimum (i.e.they had only a few more clusters).

Note that we restricted the number of operations in a PE program to n inthe previous discussions. This is reasonable since we normally do notwant to extend the PE program execution over more than one bus cycle.However, if a PE can be programmed to execute more than n operations,those operations which are not throughput-critical can be combined inlarger clusters. This further reduces the required number of PEs withoutimpacting the overall throughput.

4.2 PE Code Generation

After operator clustering, the PE program code for every cluster isgenerated; cf. the assembler code in the example in Section 3. Asimplified version of conventional register allocation is used to mapinternal connections to internal registers. The instructions can bedirectly extracted from the dataflow graph of the cluster.

5 RESULTS 5.1 PE Speed and Area

The area of a Function Folding PE is estimated to be about 15% to 25%larger than the area of the corresponding simple PE, depending on thenumber of ports and registers. For 16-bit datapaths, preliminarysynthesis results achieve a PE frequency of 400-500 MHz for a 130 runsilicon process.

5.2 Complex FIR Application Analysis

This section demonstrates the implementation of a typical DSP algorithm,a FIR filter operating on complex numbers, on Function Folding PEs.Consider one FIR filter cell which computes the output Z=X*C+Y from aconstant C and inputs X and Y. All values are complex, i.e.(Zre,Zim)=(Xre*Cre−Xim*Cim+Yre, Xre*Cim+Xim*Cre+Yim). FIG. 49A shows thecorresponding dataflow graph. It contains eight operators which can befolded to three clusters for an overclocking factor of n=4, as indicatedby the dotted boxes C11, C12, C13. FIG. 49B shows the resulting clusterdataflow graph. All clusters fully utilize the PEs, i.e. use all four PEclock cycle.

Let us now compare the silicon efficiency of an implementation on acurrent XPP device (FIRcurr) with one based on Function Folding PEs(FIRnew), As outlined above, we estimate F_(PE)=400 MHz and F_(bus)=100MHz for n=4. F_(bus) is also the operating frequency of the currentarchitecture. Filters built from the given FIR cells can easily be fullypipelined for both implementations, as can be seen from FIGS. 49A and49B. Hence both implementations have the same performance: They generateoutputs at a rate of 100 MHz.

The area of a Function Folding PE is estimated asA_(FFPE)=1.2×A_(currPE), i.e. 20% larger than current PEs. The arearatio for the two filter implementations is as follows:

$\frac{A_{FIRnew}}{A_{FIRcurr}} = {\frac{3 \times A_{FFPE}}{8 \times A_{currPE}} = {\frac{3 \times 1.2 \times A_{currPE}}{8 \times A_{currPE}} = 0.45}}$

This rough estimation shows that the new implementation is more thantwice as area-efficient as the old one without requiring more pipeliningregisters in the external busses. The overall silicon efficiency is morethan doubled.

5.3 Benchmark Mapping Results

In order to determine the general applicability of Function Folding, thealgorithm described in Section, 4.1 was applied to a benchmark of 43legacy XPP configurations from a wide range of application areas. Wedetermined the average cluster utilization, i.e. the number of PE cyclesbeing used by the repetitive PE program. This value is a good indicationof the effectiveness of Function Folding. Note that a high clusterutilization does not guarantee that the PE program can be executed everybus cycle. The overall PE utilization in an application also depends onthe availability of input data and on the overall throughput of all PEs.

Table 1 shows the results for n=2 and n=4 with varying port numbers. Thenumber of internal registers was not yet restricted for this evaluation.The results for four input and output data and event ports (1.78 for n=2and 3.05 for n=4) show that the Function Folding PE resources can beexploited efficiently for average XPP configurations. The table showsthat using six data ports increases the cluster utilization onlyinsignificantly. On the other hand, using fewer data ports distinctlydecreases the utilization. We will combine hardware implementationresults detailing the area requirements of the ports with the clusterutilization numbers to determine the PE parameters which yield the bestoverall silicon efficiency.

TABLE 1 Average cluster utilization (CU) in XPP benchmark, n:overclocking factor; DI/DO: number of data input/output ports; EI/EO:number of event input/output ports. n DI DO EI EO CU 2 6 6 4 4 1.79 2 44 4 4 1.78 2 2 2 4 4 1.57 2 4 4 2 2 1.75 2 2 2 2 2 1.53 4 6 6 4 4 3.06 44 4 4 4 3.05 4 2 2 4 4 2.25 4 4 4 2 2 2.80 4 2 2 2 2 2.12

6 RELATED WORK

Though there are several projects on reconfigurable arithmetic arrays asmentioned in Section 1, to our knowledge there are no solutions similarto Function Folding in the literature. The following architecturesdiffer considerably from our approach, but also allow to quickly changethe operations performed by a PE.

The RAW microprocessor (see M. B. Taylor et al., “The RawMicroprocessor: A Computational Fabric for Software Circuits andGeneral-Purpose Programs,” IEEE Micro, March/April 2002) also contains acluster of processing elements, but they are rather complex processors.Therefore their programs cannot be generated automatically as easily asthe Function Folding PE programs. The RAW architecture resembles more amultiprocessor on a chip.

On the other hand, the MorphoSys architecture (see Lee et al.) follows aSIMD approach. All PEs in a row or column are controlled by a (global)program and execute the same instruction. This makes the PEs simpler,but the SIMD principle considerably restricts the available computationswhich can be executed. The array is also much harder to program.

Finally, multi-context devices provide two or more completeconfiguration contexts (see B. Salefski et al., “Re-configurableComputing in Wireless, In Proc. 38th Design Automation Conference, LasVegas, Nev., June 2001). This technique is adapted from multi-contextFPGAs. However, it does not allow frequent reconfigurations since theshadow configurations first have to be loaded completely. Theconfigurations are completely independent. Multicontext devices hide theconfiguration latency to a certain extent, but do not overcome thegeneral efficiency problems of coarse-grain reconfigurablearchitectures.

7 CONCLUSIONS AND FUTURE WORK

We have presented the architecture and functionality of the FunctionFolding Processing Element for an enhanced PACT XPP architecture.Preliminary analyses of both a hardware implementation and applicationsmapped to this architecture indicate that Function Folding significantlyincreases the silicon efficiency compared to current reconfigurablearithmetic arrays and has the potential to reduce the power consumption.

After the implementation of a Function Folding PE and the analysis ofits parameters, future work will include the evaluation of paths whichare not throughput-critical as mentioned at the end of Section 4.1.Integrated clustering and place-and-route algorithms will be explored.We also consider developing a direct compiler from C to Function FoldingPEs which might exploit their capabilities better then the currentdesign flow via NML.

1. Apparatus comprising: a plurality of coarse-grained data processingelements arranged in rows and columns; an interconnect structure,comprising: a plurality of global, multi-bit interconnects globallyinterconnecting the plurality of coarse-grained data processingelements; and a plurality of direct, multi-bit direct interconnects,wherein an output of a first data processing element is interconnectedto an input of an adjacent data processing element.
 2. Apparatusaccording to claim 1, wherein each of the plurality of coarse-graineddata processing elements comprises: an arithmetic unit having at leastone multiplier and at least one adder; a plurality of data inputs and aplurality of data outputs connected to the global, multi-bitinterconnect; and a plurality of data registers, wherein a) a firstsubset of the plurality of data registers are connected to the datainputs, b) a second subset of the plurality of data registers areconnected to store internal data, c) a third subset of the plurality ofdata registers are connected for data output.
 3. Apparatus according toclaim 1, wherein at least one input register of a first coarse-graineddata processing element of said plurality of coarse-grained dataprocessing elements is directly connected to an input of an adjacentcoarse-grained data processing element of said coarse-grained dataprocessing elements via an output of the first coarse-grained dataprocessing element.
 4. Apparatus according to claim 2, wherein at leastone of the direct, multi-bit, interconnects of said plurality of direct,multi-bit interconnects bypasses the arithmetic unit of at least one ofthe plurality of coarse-grained, data processing elements.
 5. Apparatusaccording to claim 1, wherein at least one input register of a firstcoarse-grained data processing element of said plurality ofcoarse-grained data processing elements is directly connected to aninput of an adjacent coarse-grained data processing element of saidcoarse-grained data processing elements via an output register of thefirst coarse-grained data processing elements.
 6. Apparatus according toclaim 1, wherein the direct, multi-bit interconnects are configured fortransmitting FIR filter data.
 7. A configurable data processing devicecomprising: an array of configurable cells; and a global configurablenetwork interconnecting the configurable cells for transferring dataglobally including the transfer of data between configurable cells;wherein: each of at least some of the configurable cells is configurablein function and comprises a data processing unit that includes amultiplier, at least two input registers and at least one outputregister; and for each of a number of pairs of adjacent ones of the atleast some of the configurable cells, in addition to the globalconfigurable network interconnection, a next neighbor connection isprovided between the adjacent cells of the pair, allowing for a directnext neighbor data transfer between the adjacent cells of the pair andbypassing the global configurable network.
 8. The configurable dataprocessing device according to claim 1, wherein the next neighborconnection is a direct connection from a cell output to a cell input ofan adjacent cell without a connection to the global configurablenetwork.
 9. The configurable data processing device according to claim2, wherein the adjacent cells connected via the next neighbor connectionare two configurable cells a first configurable cell physically disposedin direct contact with a second configurable cell.
 10. Apparatuscomprising: an array of data processing cores; a bus structureinterconnecting the array of data processing cores; wherein each of thecores is adapted for receiving and executing opcodes and processing aspart of a sequence a plurality data words.
 11. Apparatus according toclaim 10, wherein each of the array of data processing cores is adaptedfor SIMD operations.
 12. Apparatus according to claim 10, wherein eachof the array of data processing cores comprises an ALU to execute atleast one of ADD, SUB, and MUL instructions.
 13. Apparatus according toclaim 10, wherein each of the array of data processing cores comprisesan ALU to execute count-leading-zeros (CLZ) instruction.
 14. Apparatusaccording to claim 10, where each of the array of data processing corescomprises an internal register file.
 15. Apparatus according to claim10, further comprising at least one internal data register file. 16.Apparatus according to claim 10, wherein each of the array of dataprocessing cores comprises a program counter.
 17. Apparatus according toclaim 10, further including at least one program counter.
 18. Apparatusaccording to claim 10, wherein each of the data processing corescomprises multiple execution stages.
 19. Apparatus according to claim18, wherein the multiple execution stages comprises fetch, the code andexecute.
 20. Apparatus according to claim 10, further comprisingmultiple execution stages.
 21. Apparatus according to claim 20, whereinthe multiple execution stages comprises fetch, the code and execute. 22.Apparatus according to claim 10, wherein each of the array of dataprocessing cores conditionally executes instructions by testing an ALUflag, and depending upon the state of the ALU flag, either executing oromitting the execution of an instruction.
 23. Apparatus according toclaim 10, further comprising were in one or more of the array of dataprocessing cores are responsive to a wait command.
 24. Apparatusaccording to claim 23, wherein the way command is adapted to stopexecution into a specific event fulfills a specific condition. 25.Apparatus according to claim 10, further including a microprocessor, acache and a register interface, wherein said the array of dataprocessing cores and said bus structure are connected to saidmicroprocessor via said cache and register interface.
 26. Apparatusaccording to claim 10, further including a clock having a configurablefrequency.
 27. Apparatus according to claim 26, further comprising avoltage control responsive to said configurable frequency.
 28. Apparatusaccording to claim 10, wherein at least some of the data processingcores is adapted to repeatedly process the received instructions.